The Peripheral Component Interconnect-Express (herein referred to as “PCI Express” or “PCIe”) architecture utilizes a high-performance I/O (“input/output”) bus to interconnect peripheral devices in applications, such as computing and communications platforms. A system employing a PCI Express architecture supports chip-to-chip interconnect and board-to-board interconnect via cards and connectors. More specifically, a PCI Express architecture implements one or more serial, point-to-point type interconnects for communications between two devices. Additionally, multiple PCI Express devices can be connected using switches that fan out the buses, making it possible to connect a large number of devices together in a system.
PCI Express systems are based on having a root complex (“RC”) device (also referred to herein as simply a “root complex” or a “PCI Express root complex”) and one or more endpoints. However, if a problem occurs in the root complex device so that it does not function correctly, then this affects the entire PCI Express system, causing major issues (e.g., the peripheral devices are not able to perform their required operations). Using a redundant root complex in such a system has only been possible if an external PCI Express bridge device is used to allow the system to function correctly. However, such an implementation adds cost, requires additional circuit board space, and introduces significant complexity to the system.
Many networking and industrial users of PCI Express systems need fault tolerant systems that allow for redundancy. Therefore, it would be beneficial to implement a system-level redundancy in a PCI Express system so that a backup PCI Express root complex is able to come online and take over in the event the primary root complex fails.